TFE4141: Design of Digital Systems 1
Object classes and Data types
- Object classes
- Permanently defined value
- Values change after a delay ∆ or an explicitly declared delay
- Values change immediately (no ∆)
- Longterm storage of data
- Loaded when the model is run
- Write to files to store results from simulations
- Signed / Unsigned
- Integer / Natural
Physical types (Time)
- Syntax: type T_MY_TYPE is (val_1, val_2, val_3)
Finite State Machine (FSM)
Time and simulations
Microarchitecture and Block diagrams
«How do we efficiently design a digital system of the desired quality, that meets the customer needs?»
- Capture requirements
- Write specification
- Write code
- Implement (synthesis+place+route+floor plan)
- Verification metrics: Code coverage, functional coverage, pass rate
- Formal verification
- Code standards followed
- Code reviews done
- Cost effective
- With high return on the investments
- Requiremens must be met.
- Validation ensures that the product actually satisfy the customer needs.
Low power design techniques
Power usage in an FPGA is divided into two part, static and dynamic.
The dynamic energy consumed by an FPGA is the energy consumed as a consequence of tranisistors switching state (
The dynamic power is found by using:
Here "a" is the activity factor and f is the switching frequency.
Lowering the clock rate reduces dynamic power usage, but it will not reduce the dynamic energy needed for a task requiring N transitions. As the task takes longer it will use more static energy and therefore increase the total energy needed for the aforementioned task. See "Race to Halt"
The static energy is the energy consumed by the FPGA even if no transistors change state. This consumption is mainly due to transistor leakage. The static power can be found from the following equation:
The following subsections describe different ways of reducing dynamic or static power. The text in the paranthesis indicate which is reduced.
Clock gating (Dynamic)
Don't propagate the clock signal to idle sections of the fabric. This reduces dynamic power/energy as we reduce the amount of transistors switched in unused sections.
Power gating (Static)
This technique is based around using a single transistor for turning of
- Header switch (PMOS turning off access to power)
- Lower leakage for PMOS than NMOS
- Larger area than footer
- Footer switch (NMOS turning off access to ground)
- Smaller area than header
- Higher leakage for NMOS than PMOS
- Susceptible to ground noise
"Race to Halt" (Static)
Increasing the dynamic power consumption for a short duration so that we can complete the task faster and then enter low-power sleep mode (Using power gating), lowering the static power consumption. This works best for systems where the idle period between actions is comparatively long, or the static power consumption is a large portion of the total even when not idle. The idea behind this trade-off is of course to lower the total energy consumption.
The purpose of production testing is
Controllability & Observability
Controllabilty is how easily we are able to control the value of an internal signal, while observability is how easily we may observe the value of an internal signal. Both are concidered with only access to the circuits inputs and outputs.
Faults come in iether spot defects or distributed defects. Typical spot defects are short-circuits or open-circuits. There are two fault models discussed in this course: Stuck-at Fault Model Path-Delay Fault Model
Stuck-at Fault Model
This is the most widely used fault model. It tests if a signal is stuck at either 0 or 1. (S-A-0 or S-A-1) Because of this it models spot defects. It assumes that only one input on one gate will be faulty at a time.
Path-Delay Fault Model
|# Modelled Faults|
|# Detected Faults|
|M||Plain text (Message)|
|e||Exponent (Public key)|
|d||Exponent (Private key)|
|n||Dividend (In Public key)|
- Event: A signal changes value