# Introduction ## Disclaimer This compendium is a work in progress and needs review and possibly restructuring and citations. The current structure is based on the ordering and naming of lectures from the 2017 semester. ## Specialization course This subject is part of the [Design of Digital Systems, Specialization Course (TFE4525)](https://www.wikipendium.no/TFE4525_Design_of_Digital_Systems_Specialization_Course). # Fundamentals ## Power dissipation Power dissipation in CMOS circuits are typically divided into three components, namely _static power_, _dynamic power_ and _short-circuit power_. ### Static power dissipation Mostly the power dissipated through leakage currents. $$ P_s = V_{DD} \times I_D, $$ where $V_{DD}$ is the supply voltage and $I_D$ is the leakage current. ### Dynamic power dissipation Power from switching logic by charging and discharging in capacitors. $$ P_d = \alpha f_{CLK} C_L V_{DD}^2, $$ where $\alpha$ is the activity factor, $f_{CLK}$ is the clock frequency, $C_L$ is the swithing load capacitance, and $V_{DD}$ is the supply voltage. ### Short-circuit power dissipation Caused by transients in switching in the window when p-channel and n-channel of eg. and inverter connects the supply voltage to ground. This power is arguably related to the activity factor of the circuit and hence a part of the dynamic power dissipation. ## Delay, power and energy Tightly intertwined in CMOS VLSI. Can be illustrated by theoretically adjusting factors in the above equations. By for instance lowering the frequency of a system you will obtain a lower dynamic power, however since power is just a measure of energy per time unit the total energy to perform a task in the same amount of clock cycles may change due to the circuits static power dissipation, glitches, etc. # Ultra low voltage and low power circuit design techniques Power dissipation in CMOS circuits can be reduced by lowering the supply voltage. This is easily illustrated with the quadratic nature of the supply voltage metric in the _dynamic power equation_. The tradeoffs of this approach includes the fact that the threshold voltage $V_{Th}$ of the transistors needs to be below $V_{DD}$ which makes the circuit more prone to errors related to noise (lower $SNR$). ## Methods ### Sub-threshold circuits $$V_{DD}(t) < V_{Th}, \quad \forall t$$ Transistors are never saturated and hence differentiating binary values requires precise measurements and comparatively low noise levels. The benefit to this method is the obvious advantages to lowering $V_{DD}$ just by looking at the static and dynamic power formulas. ### Threshold voltage differentiation Power dissipation may be reduced by increasing the threshold-voltages of transistors outside a systems critical path. As long as the increased delay of these transistors do not add constraints on max frequency the circuit will save power compared its non-differentiated counterpart because increased delay reduce leakage current. ### Adaptive voltage scaling Depending on the work-load of a system there may be dead time. This can be exploited by identifying these windows and reducing the supply voltage accordingly in order to reduce power dissipation at the cost of reduced frequency and will usually reduce the overall energy needed to complete each task. This can even be applied during production of a circuit, exploiting performance variance in order to let a closed loop determine the needed supply voltage for each individual circuit. # Razor flip-flops

# HDL techniques for low power design ... # Brain-inspired chips for large data sets ... # Ultra-low power wireless microcontroller design ... # Energy scavenging ... # Low power FPGAs ... # Moore's law and technology scaling ... # Cloud computing ...