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Table of Contents
  1. Introduction
    1. Disclaimer
    2. Specialization course
  2. Fundamentals
    1. Power dissipation
      1. Static power dissipation
      2. Dynamic power dissipation
      3. Short-circuit power dissipation
    2. Delay, power and energy
  3. Ultra low voltage and low power circuit design techniques
    1. Methods
      1. Sub-threshold circuits
      2. Threshold voltage differentiation
      3. Adaptive voltage scaling
  4. Razor flip-flops
    1. Components
      1. Shadow Latch
      2. Meta-stability detector
    2. Canary flip-flops
    3. Bubble razor flip-flops
  5. HDL techniques for low power design
  6. Brain-inspired chips for large data sets
  7. Ultra-low power wireless microcontroller design
  8. Energy scavenging
  9. Low power FPGAs
  10. Moore's law and technology scaling
  11. Cloud computing
  12. Uncategorized topics
    1. Race-to-halt energy saving
    2. Benchmarking
    3. Programmable delay elements
  13. Acronyms
‹

TFE01: Low power digital design

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Introduction

Disclaimer

This compendium is a work in progress and needs review and possibly restructuring and citations. The current structure is based on the ordering and naming of lectures from the 2017 semester.

Specialization course

This subject is part of the Design of Digital Systems, Specialization Course (TFE4525).

Fundamentals

Power dissipation

Power dissipation in CMOS circuits are typically divided into three components, namely static power, dynamic power and short-circuit power.

Static power dissipation

Mostly the power dissipated through leakage currents.

$$ P_s = V_{DD} \times I_D, $$

where $V_{DD}$ is the supply voltage and $I_D$ is the leakage current.

Dynamic power dissipation

Power from switching logic by charging and discharging in capacitors.

$$ P_d = \alpha f_{CLK} C_L V_{DD}^2, $$ where $\alpha$ is the activity factor, $f_{CLK}$ is the clock frequency, $C_L$ is the swithing load capacitance, and $V_{DD}$ is the supply voltage.

Short-circuit power dissipation

Caused by transients in switching in the window when p-channel and n-channel of eg. and inverter connects the supply voltage to ground.

$$ P_{SC} = V_{DD} \times I_{SC} $$

This power is arguably related to the activity factor of the circuit and hence a part of the dynamic power dissipation.

Delay, power and energy

Tightly intertwined in CMOS VLSI. Can be illustrated by theoretically adjusting factors in the above equations. By for instance lowering the frequency of a system you will obtain a lower dynamic power, however since power is just a measure of energy per time unit the total energy to perform a task in the same amount of clock cycles may change due to the circuits static power dissipation, glitches, etc.

$$ Power = (1 - \beta)Length^2 + \beta(Gates) $$

Power delay product: $\text{PDP} = \text{Power} \times \text{Delay} = \text{Enegy} $

Energy delay product: $\text{EDP} = \text{PDP} \times \text{Delay} = \text{Power} \times \text{Delay}^2$

Ultra low voltage and low power circuit design techniques

Power dissipation in CMOS circuits can be reduced by lowering the supply voltage. This is easily illustrated with the quadratic nature of the supply voltage metric in the dynamic power equation. The tradeoffs of this approach includes the fact that the threshold voltage $V_{Th}$ of the transistors needs to be below $V_{DD}$ which makes the circuit more prone to errors related to noise (lower $SNR$).

Methods

Sub-threshold circuits

$$V_{DD}(t) < V_{Th}, \quad \forall t$$

Transistors are never saturated and hence differentiating binary values requires precise measurements and comparatively low noise levels. The benefit to this method is the obvious advantages to lowering $V_{DD}$ just by looking at the static and dynamic power formulas.

Threshold voltage differentiation

Power dissipation may be reduced by increasing the threshold-voltages of transistors outside a systems critical path. As long as the increased delay of these transistors do not add constraints on max frequency the circuit will save power compared its non-differentiated counterpart because increased delay reduce leakage current.

Adaptive voltage scaling

Depending on the work-load of a system there may be dead time. This can be exploited by identifying these windows and reducing the supply voltage accordingly in order to reduce power dissipation at the cost of reduced frequency and will usually reduce the overall energy needed to complete each task. This can even be applied during production of a circuit, exploiting performance variance in order to let a closed loop determine the needed supply voltage for each individual circuit.

Razor flip-flops

Read more

Why: Eliminate timing margins by detecting and correcting transient delay errors.

How: Replace critical flip-flops with flip-flops enabled to detect late arriving signals and use architectural replay to correct errors.

Due to architectural invasiveness (overhead) they are not fully implemented on commercially available processors. Also introduction of significant hold time constraints make it difficult to meet worsening timing variability.

Components

Shadow Latch

Shadow latch

Source: "Time redundant parity for low-cost transient error detection" on ResearchGate

  • Controlled using delayed clock
  • Operating voltage constrained such that worstcase delay is guaranteed to meet setup time
  • Different outputs from main flip-flop and shadow latch means delay error

Meta-stability detector

Detects meta-stability ($V \approx \frac{V_{DD}}{2}$) and may be used to identify an error.

Canary flip-flops

  • Fails at higher supply voltages than other flip-flops.
  • Benefits: Higher fail rate than core flip-flops make them suitable as indicators for reaching minimal voltage in eg. adaptive voltage scaling.

Bubble razor flip-flops

Uses a novel error-detection technique based on two-phase latch timing and a local replay mechanism that can be inserted automatically in any design. [Fojtik et al. 2012]

  • Benefits: Solves short path problem and error-recovery for chains of dependent sequential elements.

HDL techniques for low power design

  • Resource sharing
  • Clock gating
  • State machine coding (gray, one-hot etc.)
  • Avoiding runaway counters
  • Minimizing transitions
  • Bus invert coding
  • (automatic optimizations done by synthesizer)

Brain-inspired chips for large data sets

  • Not Von Neumann architecture
    • Emulate neurons and synapses
    • Event driven
    • Memory locality with many lightweight cores
  • Good for:
    • Large data sets with parallel data
      • Image processing
        • Surveillance
    • Pattern recognition
      • Speech recognition
    • Machine-learning and artificial intelligence
  • Example: IBM TrueNorth

Ultra-low power wireless microcontroller design

...

Energy scavenging

...

Low power FPGAs

...

Moore's law and technology scaling

...

Cloud computing

Reduce overall power needed for computation by providing on-demand access to hardware and software.

Uncategorized topics

Race-to-halt energy saving

Benchmarking

Programmable delay elements

  • Paper

Acronyms

AVS Adaptive Voltage Scaling
CMS Cloud Management System
DVS Dynamic Voltage Scaling
DVFS Dynamic Voltage and Frequency Scaling
HPM Hardware Performance Monitor
PDE Programmable Delay Element

Written by

larshb marthauk
Last updated: Wed, 29 Nov 2017 15:35:14 +0100 .
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