Static power dissipation

Mostly the power dissipated through leakage currents.

$$ P_s = V_{DD} \times I_D, $$

where $V_{DD}$ is the supply voltage and $I_D$ is the leakage current.

Dynamic power dissipation

Power from switching logic by charging and discharging in capacitors.

$$ P_d = \alpha f_{CLK} C_L V_{DD}^2, $$ where $\alpha$ is the activity factor, $f_{CLK}$ is the clock frequency, $C_L$ is the swithing load capacitance, and $V_{DD}$ is the supply voltage.

Short-circuit power dissipation

Caused by transients in switching in the window when p-channel and n-channel of eg. and inverter connects the supply voltage to ground.

$$ P_{SC} = V_{DD} \times I_{SC} $$

This power is arguably related to the activity factor of the circuit and hence a part of the dynamic power dissipation.

Sub-threshold circuits

$$V_{DD}(t) < V_{Th}, \quad \forall t$$

Transistors are never saturated and hence differentiating binary values requires precise measurements and comparatively low noise levels. The benefit to this method is the obvious advantages to lowering $V_{DD}$ just by looking at the static and dynamic power formulas.

Threshold voltage differentiation

Power dissipation may be reduced by increasing the threshold-voltages of transistors outside a systems critical path. As long as the increased delay of these transistors do not add constraints on max frequency the circuit will save power compared its non-differentiated counterpart because increased delay reduce leakage current.

Adaptive voltage scaling

Depending on the work-load of a system there may be dead time. This can be exploited by identifying these windows and reducing the supply voltage accordingly in order to reduce power dissipation at the cost of reduced frequency and will usually reduce the overall energy needed to complete each task. This can even be applied during production of a circuit, exploiting performance variance in order to let a closed loop determine the needed supply voltage for each individual circuit.

Shadow Latch

Source: "Time redundant parity for low-cost transient error detection" on ResearchGate

• Controlled using delayed clock
• Operating voltage constrained such that worstcase delay is guaranteed to meet setup time
• Different outputs from main flip-flop and shadow latch means delay error

Meta-stability detector

Detects meta-stability ($V \approx \frac{V_{DD}}{2}$) and may be used to identify an error.