Why do we use programmable circuits?

Microcontrollers are cheap, quite flexible, can be designed to be very power-efficient, and are easy to use. Disadvantages of microcontrollers are that they are sequential and have limited processing speed. They rarely have the ability to handle large amounts of data and are made to be very general, which on one hand makes them versatile, but they cannot be used for more specialized applications.

Especially in systems such as video and audio processing (graphics), cryptography, and AI (matrix operations), it is important to design systems that are equipped to handle larger amounts of computation.

Programmable circuits are chips where the hardware can be programmed.

Advantages of these are that they are very flexible and suitable for a wide range of applications. They are fast and good for implementing parallelism. The disadvantages of these are that they are relatively expensive, more complex, and have higher power consumption.

Lookup Table (LUT)

The lookup table, LUT (LookUp Table), is used to implement logic functions, i.e., combinational circuits. An "LUT" (lookup table) is a lookup table that is a realization of a combinational expression where each word in the lookup table / memory specifies the output value, and the input values select the correct bit value using a multiplexer structure. It is generally the number of inputs (bits) that determines the number of LUTs for combinational circuits, not the complexity of the system.

Memory cells (RAM) are used to "store" the truth table of a logic function. The address of the memory represents the input values to the function.

Coding Practices

A signal and variable are assigned as follows:

Signal: <=, e.g., sig <= 0; Variable: :=, e.g., var := 0;

Code lines begin with --, block comments are written with /* */

Operators

• Highest precedence first, left to right within same precedence group, use parenthesis to control order.
• Unary operators take an operand on the right.
• "result same" means the result is the same as the right operand.
• Binary operators take an operand on the left and right.
• "result same" means the result is the same as the left operand.

** exponentiation, numeric ** integer, result numeric

abs absolute value, abs numeric, result numeric

not complement, not logic or boolean, result same

* multiplication, numeric * numeric, result numeric

/ division, numeric / numeric, result numeric

mod modulo, integer mod integer, result integer

rem remainder, integer rem integer, result integer

+ unary plus, + numeric, result numeric

- unary minus, - numeric, result numeric

+ addition, numeric + numeric, result numeric

- subtraction, numeric - numeric, result numeric

& concatenation, array or element & array or element, result array

sll shift left logical, logical array sll integer, result same

srl shift right logical, logical array srl integer, result same

sla shift left arithmetic, logical array sla integer, result same

sra shift right arithmetic, logical array sra integer, result same

rol rotate left, logical array rol integer, result same

ror rotate right, logical array ror integer, result same

= test for equality, result is boolean

/= test for inequality, result is boolean

< test for less than, result is boolean

<= test for less than or equal, result is boolean

> test for greater than, result is boolean

>= test for greater than or equal, result is boolean

and logical and, logical array or boolean, result is same

or logical or, logical array or boolean, result is same

nand logical complement of and, logical array or boolean, result is same

nor logical complement of or, logical array or boolean, result is same

xor logical exclusive or, logical array or boolean, result is same

xnor logical complement of exclusive or, logical array or boolean, result is same

Taken from University of Maryland. Another useful source.

Naming Conventions

Names for signals, variables, entities, packages, etc., have a set of rules for how they can be written.

• Can contain letters between a-z (A-Z), digits (0-9)
• Must start with a letter
• Must be different from reserved words
• Cannot contain two or more underscores next to each other and cannot end with an underscore ("__")

Design Flow in VHDL

1. Analysis and processing: The code is checked for errors and creates an RTL-level representation

2. Simulation: Test that the circuit behaves as it should

3. Synthesis: Translation to circuit representation

4. Place and Route (P&R): Implementation, the circuit is adapted to the device to be used (De10-Lite)

5. Timing analysis

6. Programming

7. Test on hardware (HW)

Structure of a VHDL Design

Illustration showing a VHDL design divided into packages, interface (entity), and circuit description (architecture).

Concurrent versus Sequential Statements

An important principle in hardware description languages, including VHDL, is concurrency. - In digital circuits, everything happens simultaneously. - This is reflected in VHDL by allowing statements to be written in any order. - But a given signal can only be assigned a value once. - Exception: Certain code structures (processes and subprograms) are interpreted line by line but are always concurrent in relation to the rest of the code.

Processes are concurrent with respect to all other statements, but internally a process is sequential (only statements in (b)). Statements are inherently concurrent (parallel)sequential inside PROCESS, FUNCTION or PROCEDURE.

Object Classes in VHDL

An object is an entity that has a value of a data type. There are four object classes in VHDL. • Constant: Only readable, cannot be changed. • Signal: Used for signaling between processes. • Variable: Only for internal use in a process, procedure or function. • File: Only used in testbenches (not hardware).

Data Types

• VHDL: Strongly typed language.
• Does not allow data transfer between objects of different types (even if they are identically declared).
• Appropriate casting functions must be used.
• Does not allow implicit type conversion.
• Every operator is constructed for specific data types.
• Types can be predefined or user-defined.
• It is allowed to define your own data types in VHDL
• It is not possible to define signals with the type real during hardware synthesis
• The data type bits defined by '0' and '1'. Note that std_logic has multiple definitions.
• Boolean → 1 bit
• Integer → 64 bit/32 bit

Aggregation and Concatenation

• Putting data pieces together to form or enlarge data arrays.

signal s1, s2, s3, s4: std_logic_vector(3 downto 0);

s1 <= ('1','0','1','0') -- Aggregation: s1="1010"

s2 <= ('1','0',others => 'Z'); -- Aggregation: s2="10ZZ"

s3 <= "11" & "00"; -- Concatenation: s3="1100"

s4 <= '1' & s3(3 downto 1); -- Concatenation: s3="1110"

Subprograms

Moore

In Moore state machines, the output of the state machine is only dependent on the current state of the state machine. Input only affects transitions between different states.

Mealy

In Mealy state machines, the output is dependent on both the current state and the input. (Output changes with transitions between states, not the state itself.)

Main Differences Between Moore and Mealy

(Taken from Scott Davis (2025))

Examples of State Machines (Clocked and Combinatorial)

The entity and architecture can be declared similarly. In the architecture, one defines a custom type for the different states, and uses a signal to store the state value.

Assert

• Main purpose: Checking the design.
• Used in testbenches.
• Does not infer any hardware.
• Can be used in both sequential and combinatorial code.
• The message (static and/or dynamic) is displayed when the condition is false.

[label:] assert condition [report message] [severity level];

Dealing with Time in VHDL

• Major difference between code for synthesis and simulation: The presence of time in the latter.

• Useful constructions for testbenches related to time:

• wait for The process waits for a specific time.

• after An action is scheduled after a specific time.

• now Returns the current simulation time.

• S'stable(t) Attribute, returns true if no events have occurred on signal S during the last t time units (looks backwards).

• S'last_event Attribute, returns the time since last event on S.

-S'transaction Attribute, causes a bit to toggle when a transaction (future event) on signal S is scheduled.

Examples of Simple Expressions

The system described in wait expressions:

p_test1: process is

begin

test1 <= '1';

wait for 20 ns;

test1 <= '0';

wait for 10 ns;

end process p_test1;

p_test2: process is

begin

test2 <= '0';

wait for 30 ns;

test2 <= '1 ';

wait;

end process p_test2;

Sequential Logic versus Combinatorial Logic

Digital logic has two main categories; combinatorial logic, where changes happen immediately, and clocked logic, where changes happen at a clock edge. Clocked logic is also called sequential logic. The difference between clocked logic and combinatorial logic is that clocked logic contains memory in the form of flip-flops, thus it is not necessary in the code to assign all signals every time, as in combinatorial logic. Clocked logic is dependent on the system's previous values/states. Clocked logic is built up of flip-flops, which update outputs on each edge of a clock signal. Combinatorial logic is realized with logic gates. Combinatorial logic requires no knowledge of the system's previous state, while sequential logic is dependent on knowing the system's previous state.

Latches and Flip-Flops

• Latches and flip-flops are "registers". They are units for storing information.
• Latches → level-sensitive, transparent when clk is high, opaque when clk is low.
• Flip-flops → edge-sensitive, transparent at clock transitions

If one wants a combinatorial circuit without a latch, one must ensure that variables are always assigned a value in or before an if-statement, or include an "else" in the code. If a variable is used before it is assigned in the process, one must add a register element to remember the previous value of the variable. Make a table to check if all signals in an if-loop are assigned a value!

• A signal must always be assigned a value in concurrent processes or else latches will be inferred (combinatorial loops).
• Make sure to use others and remember that std_logic has more possible values than ‘0’ and ‘1’.
• We don’t want latches.
• If using the if statement in a process all combinations must be covered for concurrent logic.
• Not necessary for sequential logic.
• Do not use unaffected in combinatoric logic → Latches

Hexadecimal

Hexadecimal is a number system that contains 16 different ways to represent numbers, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F. This is called a base-16 system.

Decimal 15 is thus described as hexadecimal F. When describing e.g., 16 or 17, one starts over in the hexadecimal sequence, with 10 (decimal 16) and 11 (decimal 17).

Decimal 15 can be described as '1111' in binary, and this makes hexadecimal used as a method to shorten expressions in binary. This is widely used to analyze signals to save space and write shorter code.

In VHDL, one can write a hexadecimal number as X"AD", which is equal to the more common naming convention in C, 0xAD.

Decoding hexadecimal to binary was an exam question from an earlier similar subject, and the way to do it is as follows:

One splits the number "AD" into its parts, A and D. These can then be used to convert to decimal numbers, 10 and 13. Representing 10 in binary gives 1010 (8 + 2), and representing 13 in binary gives 1101 (8 + 4 +1). This can then be put together as "10101101", which is the binary number.

Description of a System

When describing a system, remember clock and reset. Think about overflow/underflow! When describing an entity from an interface, be aware of the number of bits on each signal.

Detect Clock Edges

• Both work for synthesis, but the rising_edge/falling_edge are recommended because:
• Checks the value before and after the clock transition.
• Works also for 'L' and 'H' values (converted to '0' and '1').
• Works also for data types bit and boolean.

if clk'event and clk = '1' then … -- Positive clock transition

if clk'event and clk = '0' then … -- Negative clock transition

if rising_edge(clk) then … -- Positive clock transition (recommended)

if falling_edge(clk) then … -- Negative clock transition (recommended)

Avoid Multiple Assignments to a Signal

• Not allowed to assign a value to a signal from several places.
• Concurrent code: Only possible to assign a signal one place, or inside one combinatoric process.
• Sequential code: A signal can be assigned several times, but only inside the same process.

Suggested Procedure for Arithmetic Circuits

• 1. If the circuit is arithmetic: Integer or floating point?
• Floating point should be avoided in VHDL due to higher usage of resources, higher power consumption and lower speed.
• 1. List all operations involved (+, -, *, /, **, rem, mod, abs) and check the constraints for each operator to be used:
• Types (unsigned or signed).
• Number of bits in the result.
• 1. How to deal with overflow:
• Extend the operands. •-Flag (must decide how to handle a flag).

Arithmetic Circuits in the VHDL code

1. Use only standard-logic data types for the circuit ports.

2. In the architecture: Convert the standard-logic vector to one of the arithmetic data types.

3. Do the computations.

4. Convert the results back to standard-logic vector on the ports.

5. Carefully simulate the design.

Component Instantiation Statements

• Declaration of the component (identical with the entity).

component component_name [is]

[generic (…);]

port (…);

end component [component_name];

• A component instantiation statement.

label: [component] component_name

[generic map (generic_association_list)]

port map (port_association_list);